Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, medical devices, automobiles, and other applications. The technology used to manufacture image sensors, and in particular complementary metal-oxide semiconductor (“CMOS”) image sensor (“CIS”), has continued to advance at a great pace. Modern image sensor applications place demands for faster processing speeds and better image quality, while simultaneously expecting miniaturization in the physical size of the image sensor. So new architectures need to be developed to improve the performance of image sensor circuits to keep place with these demands.
One option to improve performance of image sensor circuits is to improve the readout circuit for the pixel array of the image sensor. FIG. 1A is a functional block diagram illustrating an image sensor 100. Image sensor 100 includes a pixel array 110 including pixel cells 111, 112, 113 and 114, control circuitry 120, readout circuitry 130 and function logic 140. After each pixel has acquired its image data or image charge, the image data is read out to readout circuitry 130 via bit line 115. The image data from pixel cells 111, 112, 113 and 114 is readout via bit line 115 one at a time via a column amplifier 131 and then transferred to a sample and convert circuit 132. From there, it is coupled to function logic 140 via readout line 141. Function logic 140 may simply store the digital image data and/or manipulate the digital image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust control, or otherwise).
FIG. 1B is a functional block diagram illustrating greater detail of readout circuit 130. Bit line 115 couples pixel cells of a given column within pixel array 110 to column amplifier 131. Switch 151 selectively couples column amplifier 131 to sampling capacitor 152 and analog-to-digital converter (“ADC”) 154. The output of ADC 154 is coupled to function logic 140 to store digital pixel values corresponding to digital pixel signals. In this readout architecture, separate sample and conversion periods are required to read out each pixel cell in the bit line. However, the sample and conversion periods are serialized, as illustrated in FIG. 1C. Since, column amplifier 131 and switch 151 are idle during the serialized conversion periods for each pixel cell row, the total readout speed of each column of pixel array 110 is limited.